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Silicon Validation Engineer

About Aviva Links

Aviva Links is a leading startup founded by industry veterans with a solid track record of technology innovation and business execution. We are building advanced connectivity solutions for next generation autonomous systems utilizing our deep domain expertise in multi-gigabit technologies. If you are passionate about developing cutting-edge technologies and building successful products with high impact, we want to talk to you.

Job Location
San Jose, CA
(Full Time)
Job Description Summary

We are looking for a Senior Technical Lead that will drive the characterization and productization of SerDes and other High-Speed interfaces as part of Aviva’s Automotive grade products.

This is an exciting role that includes working on Pre-Silicon test mechanisms as well as defining and implementing test sequences for Post-Silicon debug and characterization across multiple platforms.

Main Job Tasks and Responsibilities
  • Drive the Infrastructure development for robust SerDes and other High-Speed interface IP integration, debug, test and characterization for multiple platforms
  • Execute on the validation plan in a timely manner using standard test equipment such as Waveform Generators, Oscilloscopes, Network Analyzers, etc and in-house tools
  • Work with designers to debug, understand and document any issues that may arise during validation and do a root cause analysis to drive closure
  • Contribute to the definition and development of high speed SerDes IP product specifications.
  • Collaborate with hardware and software teams to resolve hardware issues and optimize results
  • Collaborate with the operations team to optimize parametric yield from high volume ATE tests
  • Define and implement System level testing and characterization of High-Speed interfaces.
  • Provide engineering support to customers where needed
Minimum Required Qualifications
  • B.S./M.S. Electrical/Computer Engineering (or similar degrees)
  • 3+ years of experience in silicon validation of with high speed SerDes, mixed signal/analog/digital ICs and blocks
  • Good understanding of high speed SerDes architecture
  • Hands on experience with debug and characterization of high-speed interfaces like CSI-2, Ethernet etc
  • Must have strong debug and problem-solving skills
  • Experience with script-based test automation (Python/GPIB) and strong scripting skills in general.
  • Hands on Debug experience with high-speed oscilloscopes, BERTs, Spectrum Analyzers, Network Analyzers
Preferred Qualifications
  • Well versed in SerDes standards and interoperability issues
  • Experience in test and screening methodology for High-Speed interfaces.

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